Keyword: FPGA
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MOPOPT009 New Bunch-by-Bunch Filling Pattern Measuring System at ELSA electron, synchrotron, cavity, controls 244
 
  • A.K. Wald, K. Desch, D. Elsner, D. Proft
    ELSA, Bonn, Germany
 
  The electron accelerator facility ELSA at the University of Bonn, Germany, can accelerate and store electrons with a final energy from 0.8GeV up to 3.2GeV. To routinely determine the filling pattern in the storage ring, a new measuring system has been developed. For hadron physics experiments the filling pattern, which is influenced by the injection from the pre-accelerating synchrotron, should be as homogeneous as possible. The new measurement system should provide a real-time measurement of the filling pattern, so that the injection can be continuously optimized. Moreover, a position measurement for each individual bunch is provided, from which the two transverse and the longitudinal tunes can be deduced. To measure the bunch-by-bunch intensity and position, the signals of the existing button-type BPMs will be digitized by fast 12-bit ADCs synchronized to the 500MHz ELSA radio frequency. The fast pre-processing and intermediate storage of the data is realized with a 500MHz clocked FPGA and transfers the data to a PC for further processing. First results of measurement system developed in-house will be presented.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2022-MOPOPT009  
About • Received ※ 08 June 2022 — Accepted ※ 16 June 2022 — Issue date ※ 28 June 2022  
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TUPOST009 Online Correction of Laser Focal Position Using FPGA-Based ML Models laser, network, controls, electron 857
 
  • J.A. Einstein-Curtis, S.J. Coleman, N.M. Cook, J.P. Edelen
    RadiaSoft LLC, Boulder, Colorado, USA
  • S.K. Barber, C.E. Berger, J. van Tilborg
    LBNL, Berkeley, California, USA
 
  Funding: This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Numbers DE-SC 00259037 and DE-AC02-05CH11231.
High repetition-rate, ultrafast laser systems play a critical role in a host of modern scientific and industrial applications. We present a prototype diagnostic and correction scheme for controlling and determining laser focal position at 10 s of Hz rate by utilizing fast wavefront sensor measurements from multiple positions to train a focal position predictor. This predictor is used to determine corrections for actuators along the beamline to provide the desired correction to the focal position on millisecond timescales. Our initial proof-of-principle demonstrations leverage pre-compiled data and pre-trained networks operating ex-situ from the laser system. We then discuss the application of a high-level synthesis framework for generating a low-level hardware description of ML-based correction algorithms on FPGA hardware coupled directly to the beamline. Lastly, we consider the use of remote computing resources, such as the Sirepo scientific framework* , to actively update these correction schemes and deploy models to a production environment.
* M.S. Rakitin et al., "Sirepo: an open-source cloud-based software interface for X-ray source and optics simulations", Journal of Synchrotron Radiation 25, 1877-1892 (Nov 2018).
 
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2022-TUPOST009  
About • Received ※ 20 May 2022 — Revised ※ 14 June 2022 — Accepted ※ 15 June 2022 — Issue date ※ 23 June 2022
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TUPOPT067 Development of a Trigger Distribution System Based on MicroTCA.4 timing, electron, controls, electronics 1171
 
  • H. Maesaka, N. Hosoda, T. Inagaki, E. Iwai, T. Ohshima
    RIKEN SPring-8 Center, Hyogo, Japan
  • N. Hosoda, T. Inagaki, E. Iwai, H. Maesaka, T. Ohshima
    JASRI, Hyogo, Japan
 
  We developed a MicroTCA.4 (MTCA.4) module to generate and distribute trigger timing signals. This module has 16 LVDS inputs and 16 LVDS outputs each on the front panel and the Zone 3 connector, and 8 M-LVDS I/O’s for MTCA.4 backplane. The trigger timing of each output can be precisely adjusted with the interval of 238 MHz or 509 MHz clocks by a 24-bit counter. The timing can also be fine-tuned by ~80 ps tap delay. This module has additional 5 optical transceivers, one for receiving trigger signals from upstream and four for fanouts to downstream. A master module distributes trigger signals, trigger counts, and event data through optical links. Slave modules generate trigger output signals with appropriate delays based on the event data and the local setting for each output channel. The timing jitter was measured to be 40 ps std, which is significantly smaller than the clock period of 238 MHz or 509 MHz. This system can also distribute an alarm signal received by a slave module to take data at a faulty situation. Trigger systems with this module have been utilized in SPring-8, SACLA, and NewSUBARU and stably synchronize various accelerator components with sufficient timing accuracy.  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2022-TUPOPT067  
About • Received ※ 08 June 2022 — Accepted ※ 16 June 2022 — Issue date ※ 20 June 2022  
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TUPOTK050 Development of Zynq SoC-Based EPICS IOC for KOMAC Remote Control System controls, EPICS, Linux, linac 1330
 
  • Y.G. Song, S.Y. Cho, J.H. Kim, S.P. Yun
    KOMAC, KAERI, Gyeongju, Republic of Korea
 
  Funding: This work was supported by the KOMAC (Korea Multi-purpose Accelerator Complex) operation fund of KAERI by MSIT (Ministry of Science and ICT)
The KOMAC proton accelerator consists of a 100 MeV linear accelerator and beam lines for beam services. Devices of various form factors are used as control systems in accelerator control systems and beam diagnosis systems. With the recent upgrade of the control system, a Zynq-based control system has been developed that enables the latest technology and low cost. The Zynq-based DAQ system was developed by adopting Digilent’s Zybo z7 series board and AD7605 analog-to-digital data acquisition system. The Zybo z7 is an embedded software and digital circuit development board built around the Xilinx Zynq-7000 family. The Zynq is based on Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core ARM Cortex-A9 processor with Xilinx7-series Field Programmable Gate Array (FPGA) logic. The AD7605 is a 4-channel and 16bit ADC with 300 kSPS on all channels. The Zynq SoC-based DAQ system will be used for beam feedback control and RF signal monitoring at KOMAC. This paper introduces the development of configurations for the development of Zynq-based control systems, programmable Logic (PL) builds, and Linux and EPICS porting.
 
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2022-TUPOTK050  
About • Received ※ 08 June 2022 — Revised ※ 10 June 2022 — Accepted ※ 17 June 2022 — Issue date ※ 10 July 2022
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THIYGD1 White Rabbit Based Beam-Synchronous Timing Systems for SHINE timing, network, FEL, electron 2415
 
  • Y.B. Yan, G.H. Chen, Q.W. Xiao, P.X. Yu
    SSRF, Shanghai, People’s Republic of China
  • G.H. Gong
    Tsinghua University, Beijing, People’s Republic of China
  • J.L. Gu, Z.Y. Jiang, L. Zhao
    USTC, Hefei, Anhui, People’s Republic of China
  • Y.M. Ye
    TUB, Beijing, People’s Republic of China
 
  Shanghai HIgh repetition rate XFEL aNd Extreme light facility (SHINE) is under construction. SHINE requires precise distribution and synchronization of the 1.003086 MHz timing signals over a long distance of about 3.1 km. Two prototype systems were developed, both containing three functions: beam-synchronous trigger signal distribution, random-event trigger signal distribution and data exchange between nodes. The frequency of the beam-synchronous trigger signal can be divided according to the accelerator operation mode. Each output pulse can be configured for different fill modes. A prototype system was designed based on a customized clock frequency point (64.197530 MHz). Another prototype system was designed based on the standard White Rabbit protocol. The DDS (Direct Digital Synthesis) and D flip-flops (DFFs) are adopted for RF signal transfer and pulse configuration. The details of the timing system design, laboratory test results will be reported in this paper.  
slides icon Slides THIYGD1 [5.582 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2022-THIYGD1  
About • Received ※ 29 May 2022 — Revised ※ 10 June 2022 — Accepted ※ 15 June 2022 — Issue date ※ 17 June 2022
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